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1 ? fn6417.0 isl24026 dual 19v, 60mhz rail-t o-rail input-output operational amplifier the isl24026 is a low power, high supply voltage, rail-to-rail input-output dual amplifier. operating on supplies ranging from 5v to 19v while consuming only 3ma per amplifier, the isl24026 has a bandwidth of 60mhz (-3db) and provides common-mode input ability beyond the supply rails, as well as rail-to-rail output capability. this enables the isl24026 to offer maximum dynamic range at any supply voltage. the isl24026 also features fast slewing and settling times, as well as a high output drive capability of 65ma (sink and source). these features make the isl24026 ideal for high speed filtering and signal conditioning applications. other applications include battery-powered, portable devices and anywhere low power consumption is important. the isl24026 is available in the 8 ld hmsop package, features a standard operational amplifier pinout, and is specified for operation over a temperature range of -40c to +85c. features ? 60mhz -3db bandwidth ? power supply operating range = 5v to 19v ? low supply current (per amplifier) = 3ma ? high slew rate = 85v/s ? unity-gain stable ? beyond the rails input capability ? rail-to-rail output swing ? 140ma output short current ? pb-free (rohs compliant) applications ? tft-lcd panels ?v com amplifiers ? reference buffers ? drivers for a-to-d converters ? data acquisition ? video processing ? audio processing ? active filters ? test equipment ? battery-powered applications ? portable equipment pinout isl24026 (8 ld hmsop) top view ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL24026IUEZ bbbea 8 ld hmsop mdp0050 ISL24026IUEZ-t13* bbbea 8 ld hmsop mdp0050 *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. vs+ voutb vinb- vinb+ vs- vina+ vina- vouta 1 2 3 4 8 7 6 5 - + - + data sheet october 1, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2007. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn6417.0 october 1, 2007 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = +25c) thermal information supply voltage between v s + and v s - . . . . . . . . . . . . . . . . . . . .+20v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . v s - - 0.5v, v s +0.5v maximum continuous output current . . . . . . . . . . . . . . . . . . . 65ma maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. measured over operating temperature range. 2. slew rate is measured on rising and falling edges. 3. ntsc signal generator used. 4. parts are 100% tested at +25c. over-temperature limi ts established by characterization and are not production tested. electrical specifications v s + = +18v, v s - = 0v, r l = 1k to 9.0v, t a = +25c, unless otherwise specified. parameter description condition min (note 4) typ max (note 4) unit input characteristics v os input offset voltage v cm = 9v 3 15 mv tcv os average offset voltage drift (note 1) 7 v/c i b input bias current v cm = 9v 2 60 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -0.3 +18.3 v cmrr common-mode rejection ratio for v in from -0.3v to 18.3v 50 72 db a vol open-loop gain 0.5v v out 18.5v 60 80 db output characteristics v ol output swing low i l = -5ma 100 200 mv v oh output swing high i l = 5ma 17.8 17.9 v i sc short-circuit output current 140 ma i out continuous output current 65 ma power supply performance psrr power supply rejection ratio v s is moved from 4.5v to 18.5v 60 80 db i s total supply current no load 6.6 8.5 ma v s power supply range 4.5 19 v dynamic performance sr slew rate (note 2) 1v v out 17v, 20% to 80% 65 85 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 80 ns bw -3db bandwidth 60 mhz gbwp gain-bandwidth product 32 mhz pm phase margin 50 cs channel separation f = 5mhz 110 db d g differential gain (note 3) r f = r g = 1k and v out = 1.4v 0.16 % d p differential phase (note 3) r f = r g = 1k and v out = 1.4v 0.22 isl24026
3 fn6417.0 october 1, 2007 electrical specifications v s + = +5v, v s - = -5v, r l = 1k to 0v, t a = +25c, unless otherwise specified. parameter description conditions min (note 4) typ max (note 4) unit input characteristics v os input offset voltage v cm = 0v 3 15 mv tcv os average offset voltage drift (note 1) 7 v/c i b input bias current v cm = 0v 2 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -5.3 +5.3 v cmrr common-mode rejection ratio for v in from -5.3v to 5.3v 65 db a vol open-loop gain -4.5v v out 4.5v 80 db output characteristics v ol output swing low i l = -5ma -4.9 v v oh output swing high i l = 5ma 4.9 v i sc short-circuit output current 140 ma i out continuous output current 65 ma power supply performance i s total supply current no load 6 7.8 ma dynamic performance sr slew rate (note 2) -4.0v v out 4.0v, 20% to 80% 75 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 80 ns bw -3db bandwidth 60 mhz gbwp gain-bandwidth product 32 mhz pm phase margin 50 cs channel separation f = 5mhz 110 db d g differential gain (note 3) r f = r g = 1k and v out = 1.4v 0.17 % d p differential phase (note 3) r f = r g = 1k and v out = 1.4v 0.24 electrical specifications v s + = +5v, v s - = 0v, r l = 1k to 2.5v, t a = +25c, unless otherwise specified. parameter description condition min (note 4) typ max (note 4) unit input characteristics v os input offset voltage v cm = 2.5v 3 15 mv tcv os average offset voltage drift (note 1) 7 v/c i b input bias current v cm = 2.5v 2 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -0.3 +5.3 v cmrr common-mode rejection ratio for v in from -0.3v to 5.3v 65 db a vol open-loop gain 0.5v v out 4.5v 84 db isl24026
4 fn6417.0 october 1, 2007 output characteristics v ol output swing low i l = -5ma 100 mv v oh output swing high i l = 5ma 4.9 v i sc short-circuit output current 140 ma i out continuous output current 65 ma power supply performance i s supply current no load 6 7.8 ma dynamic performance sr slew rate (note 2) 1v v out 4v, 20% to 80% 75 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 80 ns bw -3db bandwidth 60 mhz gbwp gain-bandwidth product 32 mhz pm phase margin 50 cs channel separation f = 5mhz 110 db d g differential gain (note 3) r f = r g = 1k and v out = 1.4v 0.17 % d p differential phase (note 3) r f = r g = 1k and v out = 1.4v 0.24 electrical specifications v s + = +5v, v s - = 0v, r l = 1k to 2.5v, t a = +25c, unless otherwise specified. (continued) parameter description condition min (note 4) typ max (note 4) unit typical performance curves figure 1. input offset voltage distribut ion figure 2. input offset voltage drift 200 quantity (amplifiers) input offset voltage (mv) 0 -12 500 400 100 300 -10 -8 -6 -4 -2 -0 2 4 6 8 10 12 typical production distribution v s = 5v t a = +25c input offset voltage drift, tcv os (v/c) 1 3 5 7 9 11 13 15 17 19 21 5 quantity (amplifiers) 0 25 15 20 10 v s = 5v typical production distribution isl24026
5 fn6417.0 october 1, 2007 figure 3. input offset voltage vs temperatur e figure 4. input bias current vs temperature figure 5. output high voltage vs temperature figure 6. output low voltage vs temperature figure 7. open-loop gain vs temperature figure 8. slew rate vs temperature typical performance curves (continued) 0 0.5 input offset voltage (mv) temperature (c) -0.5 1.0 -10 -50 30 70 110 150 1.5 2.0 0 input bias current (a) temperature (c) -0.008 0.008 -0.004 -0.012 0.004 -50 -10 30 70 110 150 v s = 5v 4.88 4.90 output high voltage (v) 4.86 4.96 4.92 4.94 v s = 5v i out = 5ma temperature (c) -10 -50 30 70 110 150 -4.91 -4.87 output low voltage (v) -4.95 -4.85 -4.89 -4.93 v s = 5v i out = 5ma temperature (c) -10 -50 30 70 110 150 -50 -10 30 70 110 150 temperature (c) open-loop gain (db) 70 75 80 85 90 v s = 5v r l = 1k 75 76 slew rate (v/s) 74 78 73 72 77 v s = 5v temperature (c) -10 -50 30 70 110 150 isl24026
6 fn6417.0 october 1, 2007 figure 9. supply current per amplifier vs supply voltage figure 10. supply current per amplifier vs temperature figure 11. differential gain figure 12. differential phase figure 13. harmonic distortion vs v op-p figure 14. open loop gain and phase typical performance curves (continued) 4 8 12 16 20 4.0 3.5 3.0 2.5 2.0 1.5 supply current (ma) supply voltage (v) 2.45 2.50 supply current (ma) 2.40 2.60 2.65 2.55 2.70 v s = 5v temperature (c) -10 -50 30 70 110 150 -0.16 -0.04 differential gain (%) ire -0.18 0 -0.12 -0.06 -0.02 -0.14 0 100 200 -0.08 -0.10 v s = 5v a v = 2 r l = 1k 0.20 differential phase () ire 0 0.30 0.15 0.25 0 100 200 0.10 0.05 -80 -40 distortion (db) v op-p (v) -90 -30 -60 -50 -70 2 04610 8 v s = 5v a v = 2 r l = 1k freq = 1mhz 3rd hd 2nd hd gain (db) 60 1k frequency (hz) phase () 40 20 250 190 130 70 10 -50 10k 100k 1m 10m 100m 80 0 -20 gain phase isl24026
7 fn6417.0 october 1, 2007 figure 15. frequency response for various r l figure 16. frequency response for various c l figure 17. closed loop output impedance fig ure 18. maximum output swing vs frequency figure 19. cmrr figure 20. psrr typical performance curves (continued) v s = 5v a v = 1 c load = 0pf 100k 1m 10m 100m 5 4 3 2 1 0 -1 -2 -3 -4 -5 magnitude (normalized) (db) frequency (hz) 3k 150 1k 562 100k 1m 10m 100m 25 15 5 -5 -15 -25 v s = 5v a v = 1 r l = 1k 560pf 100pf 47pf 10pf frequency (hz) magnitude (normalized) (db) output impedance ( ) 400 350 frequency (hz) 300 250 200 0 10k 100k 100m 1m 10m 150 100 50 2 10 maximum output swing (v p-p ) frequency (khz) 0 12 6 8 4 100k 10k 1m 100m 10m v s = 5v a v = 1 r l = 1k distortion <1% cmrr (db) -15 frequency (hz) -45 -65 1k 10k 100m 1m 10m -55 100k -25 -35 0 psrr (db) -80 -60 -40 -20 psrr+ frequency (hz) 100 1k 10m 100k 1m 10k psrr- v s = 5v t a = +25c isl24026
8 fn6417.0 october 1, 2007 figure 21. input voltage noise spectral density figure 22. channel separation figure 23. small-signal overshoot vs load capacitance figure 24. settling time vs step size figure 25. peaking vs c l typical performance curves (continued) 10 100 voltage noise (nv/ hz) frequency (hz) 1 1k 100 1k 100m 1m 10m 100k 10k -60 xtalk (db) -160 -120 -100 -80 dual measured ch a to b quad measured ch a to d or b to c other combinations yield improved rejection v s = 5v r l = 1k a v = 1 v in = 110mv rms -140 frequency (hz) 1k 10k 10m 30m 1m 100k load capacitance (pf) overshoot (%) v s = 5v a v = 1 r l = 1k v in = 50mv t a = +25c 10 1k 100 100 0 40 60 80 20 -4 4 step size (v) settling time (ns) -5 5 0 2 -2 65 55 75 105 95 v s = 5v a v = 1 r l = 1k 85 3 -1 1 -3 0.1% 0.1% peaking (db) 4.0 3.5 capacitance loading (pf) 3.0 2.5 2.0 0.0 10 100 100k 1k 10k 1.5 1.0 0.5 isl24026
9 fn6417.0 october 1, 2007 figure 26. large signal trans ient response figure 27. smal l signal transient response typical performance curves (continued) 50ns/div 1v step v s = 5v t a = +25c a v = 1 r l = 1k 50ns/div 100mv step v s = 5v t a = +25c a v = 1 r l = 1k pin descriptions pin number pin name function equivalent circuit 1 vouta amplifier a output 2 vina- amplifier a inverting input 3 vina+ amplifier a non-inverting input (reference circuit 2) 4 vs- negative power supply 5 vinb+ amplifier b non-inverting input (reference circuit 2) 6 vinb- amplifier b inverting input (reference circuit 2) 7 voutb amplifier b output (reference circuit 1) 8 vs+ positive power supply v s+ gnd v s- circuit 1 v s+ v s- circuit 2 isl24026
10 fn6417.0 october 1, 2007 applications information product description the isl24026 voltage feedback amplifier is fabricated using a high voltage cmos process. it exhibits rail-to-rail input and output capability, is unity gain stable, and has low power consumption (3ma per amplifie r). these features make the isl24026 ideal for a wide range of general-purpose applications. connected in voltage follower mode and driving a load of 1k , the isl24026 has a -3db bandwidth of 60mhz while maintaining a 85v/s slew rate. the isl24026 is a dual amplifier. operating voltage, input and output the isl24026 is specified with a single nominal supply voltage from 5v to 19v or a split supply with its total range from 5v to 19v. correct operation is guaranteed for a supply range of 4.5v to 19v. most isl24026 specifications are stable over both the full supply range and operating temperatures of -40c to +85 c. parameter variations with operating voltage and/or temperature are shown in the ?typical performance curves? on page 4. the input common-mode voltage range of the isl24026 extends 500mv beyond the supp ly rails. the output swings of the isl24026 typically extend to within 100mv of positive and negative supply rails with load currents of 5ma. decreasing load currents will extend the output voltage range even closer to the supply rails. figure 29 shows the input and output waveforms for the device in the unity-gain configuration. operation is from 5v supply with a 1k load connected to gnd. the input is a 10v p-p sinusoid. the output voltage is approximately 9.8v p-p . short circuit current limit the isl24026 will limit the short circuit current to 140ma if the output is directly shorted to the positive or the negative supply. if an output is shorted indefinitely, the power figure 28. typical application circuit vcom2 open vin v feedback v feedback open vcom1 9.1k 0 0 0 1m open vdd 10f 0 0 0 vouta vina- vina+ vs- vs+ voutb vinb- vinb+ isl24026 output input 5v 5v 10s figure 29. operation with rail-to-rail input and output v s =5v t a =25c a v =1 v in =10v p-p isl24026
11 fn6417.0 october 1, 2007 dissipation could easily increase such that the device may be damaged. maximum reliability is maintained if the output continuous current never exceeds 65ma. this limit is set by the design of the internal metal interconnects. output phase reversal the isl24026 is immune to phase reversal as long as the input voltage is limited from v s - -0.5v to v s + +0.5v. figure 30 shows a photo of the output of the device with the input voltage driven beyond the supply rails. although the device's output will not change phase, the input's overvoltage should be avoided. if an input voltage exceeds supply voltage by more than 0.6v, electrostatic pr otection diodes placed in the input stage of the device begi n to conduct and overvoltage damage could occur. power dissipation with the high-output drive capability of the isl24026 amplifier, it is possible to exceed the +125c 'absolute- maximum junction temperature' under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to equation 1: where: ?t jmax = maximum junction temperature ?t amax = maximum ambi ent temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the loads, or equation 2: when sourcing, and equation 3: when sinking, where: ? i = 1 to 2 for dual and 1 to 4 for quad ?v s = total supply voltage ?i smax = maximum supply current per amplifier ?v out i = maximum output voltage of the application ?i load i = load current if we set the two p dmax equations equal to each other, we can solve for r load i to avoid device overheat. figures 31 and 32 provide a convenient way to see if the device will overheat. the maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. by using th e previous equation, it is a simple matter to see if p dmax exceeds the device's power derating curves. to ensure proper operation, it is important to observe the recommended derating curves shown in figures 31 and 32. figure 31. package power dissipation vs ambient temperature 1v 1v 10s figure 30. operation with beyond-the-rails input v s = 2.5v t a = +25c a v = 1 v in = 6v p-p p dmax t jmax t amax ? ja -------------------------------------------- - = (eq. 1) p dmax iv [ s i smax v ( s +v out i ) i load i ? + ] = (eq. 2) p dmax iv [ s i smax v ( out iv s - ) i load i ? + ] = (eq. 3) jedec jesd51-3 low effective thermal conductivity test board 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) 85 486mw j a = 2 0 6 c / w h m s o p 8 0.5 isl24026
12 fn6417.0 october 1, 2007 figure 32. package power dissipation vs ambient temperature unused amplifiers it is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. the inverting input should be direct ly connected to the output and the non-inverting input tied to the ground plane. power supply bypassing and printed circuit board layout the isl24026 can provide gain at high frequency. as with any high-frequency device, good printed circuit board layout is necessary for optimum performance. ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v s - pin is connected to ground, a 0.1f ceramic capacitor should be placed from v s + pin to v s - pin. a 4.7f tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. one 4.7f capacitor may be used for multiple devices. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. jedec jesd51-7 high effective thermal conductivity test board 1.0 0.9 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) 85 870mw j a = 1 1 5 c / w h m s o p 8 0.8 0.5 0.7 isl24026
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6417.0 october 1, 2007 isl24026 hmsop (heat-sink msop) package family 1 (n/2) (n/2)+1 n plane seating n leads 0.10 c pin #1 i.d. e1 e b detail x 3 3 gauge plane see detail "x" c a 0.25 a2 a1 l 0.25 c a b d a m b e c 0.08 c a b m h l1 end view side view top view e2 bottom view d1 exposed thermal pad mdp0050 hmsop (heat-sink msop) package family symbol millimeters tolerance notes hmsop8 hmsop10 a1.001.00 max. - a1 0.075 0.075 +0.025/-0.050 - a2 0.86 0.86 0.09 - b 0.30 0.20 +0.07/-0.08 - c0.150.15 0.05 - d 3.00 3.00 0.10 1, 3 d1 1.85 1.85 reference - e4.904.90 0.15 - e1 3.00 3.00 0.10 2, 3 e2 1.73 1.73 reference - e0.650.50 basic - l0.550.55 0.15 - l1 0.95 0.95 basic - n 8 10 reference - rev. 1 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.

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